Testing and Design for Testabiltiy
- Design for testability
- Defects, faults and errors
- Test design and fault coverage
- Stuck at fault model
- Stuck open/short fault model
- Scan Technique
- Built-in self test
- Testing memories
- IC packaing
- PCB design fabrication
- Boundry scan and JTAG
- Glitches and logical hazards
- Static Hazarads
- Dynamic Hazarads
- Reliability of vlsi systems